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infineon technologies 1 9.01 hys 64/72v32300gu sdram-modules 3.3 v 32m x 64/72-bit, 256mbyte sdram modules 168-pin unbuffered dimm modules description the hys 64v32300gu and hys 72v32300gu are industry standard 168-pin 8-byte dual in-line memory modules (dimms) which are organized as 32m 64 and 32m 72 in 1 memory bank high speed memory arrays designed with 256m synchronous drams (sdrams) for non-parity and ecc applications. the dimms use -7 speed sorted 32m 8 sdram devices in tsop54 packages to meet the pc133-222 requirement, -7.5 components for pc133-333 and -8 components for the standard pc100 applications. decoupling capacitors are mounted on the pc board. the pc board design is according to intel?s module specification. the dimms have a serial presence detect, implemented with a serial e 2 prom using the 2-pin i 2 c protocol. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes are available to the end user. all infineon 168- pin dimms provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25? (31.75 mm) height. 168 pin unbuffered 8 byte dual-in-line sdram modules for pc main memory applications using 256mbit technology. pc100-222, pc133-333 and pc133-222 versions one bank 32m 64 and 32m 72 organisation optimized for byte-write non-parity or ecc applications fully pc board layout compatible to intel?s rev. 1.0 module specification programmed latencies: single + 3.3 v ( 0.3 v) power supply programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh decoupling capacitors mounted on substrate all inputs, outputs are lvttl compatible serial presence detect with e 2 prom uses infineon 256 mbit sdram components in 32m 8 organization and tsopii-54 packages gold contact pads, card size: 133.35 mm 31.75 mm 3.00 mm (jedec mo-161-ba) product speed cl t rcd t rp -7 pc133 2 2 2 -7.5 pc133 3 3 3 -8 pc100 2 2 2 sdram performance: -7 / -7.5 -8 unit pc133 pc100 f ck clock frequency (max.) 133 100 mhz t ac clock access time 5.4 6 ns
hys 64/72v32300gu sdram-modules infineon technologies 2 9.01 note: all part numbers end with a place code designating the die revision. consult factory for current revision. example: hys 64v32300gu-8-c2, indicating rev. c2 dies are used for sdram components. ordering information type code package descriptions module height hys 64v32300gu-7-d pc133-222-520 l-dim-168-33 pc133 32m 64 1 bank sdram module 1.25 ? hys 72v32300gu-7-d pc133-222-520 l-dim-168-33 pc133 32m 72 1 bank ecc-sdram module 1.25 ? hys 64v32300gu-7.5-c2 hys 64v32300gu-7.5-d pc133-333-520 l-dim-168-33 pc133 32m 64 1 bank sdram module 1.25 ? hys 72v32300gu-7.5-c2 hys 72v32300gu-7.5-d pc133-333-520 l-dim-168-33 pc133 32m 72 1 bank ecc-sdram module 1.25 ? hys 64v32300gu-8-c2 pc100-222-620 l-dim-168-33 pc100 32m 64 1 bank sdram module 1.25 ? hys 72v32300gu-8-c2 pc100-222-620 l-dim-168-33 pc100 32m 72 1 bank ecc-sdram module 1.25 ? pin definitions and functions a0 - a12 address inputs clk0 - clk3 clock input ba0, ba1 bank selects dqmb0 - dqmb7 data mask dq0 - dq63 data input/output cs0 , cs2 chip select cb0 - cb7 check bits (x72 organisation only) v dd power (+ 3.3 v) ras row address strobe v ss ground cas column address strobe scl clock for presence detect we read/write input sda serial data out for presence detect cke0 clock enable n.c./du no connection address format part number rows columns bank select refresh period interval 32m 64/72 hys64/72v32300gu 13 10 2 8k 64 ms 7.8 s
hys 64/72v32300gu sdram-modules infineon technologies 3 9.01 note: pin names in parantheses are for the x72 ecc versions; example: pin 106 = (cb5) pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1 v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 du 86 dq32 128 cke0 3dq1 45cs2 87 dq33 129 n.c. 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 v dd 48 du 90 v dd 132 n.c. 7dq4 49 v dd 91 dq36 133 v dd 8 dq5 50 n.c. 92 dq37 134 n.c. 9 dq6 51 n.c. 93 dq38 135 n.c. 10 dq7 52 n.c. (cb2) 94 dq39 136 cb6 11 dq8 53 n.c. (cb3) 95 dq40 137 cb7 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v dd 101 dq45 143 v dd 18 v dd 60 dq20 102 v dd 144 dq52 19 dq14 61 n.c. 103 dq46 145 n.c. 20 dq15 62 du 104 dq47 146 du 21 n.c. (cb0) 63 n.c. 105 n.c. (cb4) 147 n.c. 22 n.c. (cb1) 64 v ss 106 n.c. (cb5) 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 n.c. 66 dq22 108 n.c. 150 dq54 25 n.c. 67 dq23 109 n.c. 151 dq55 26 v dd 68 v ss 110 v dd 152 v ss 27 we 69 dq24 111 cas 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 cs0 72 dq27 114 n.c. 156 dq59 31 du 73 v dd 115 ras 157 v dd 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 clk2 121 a9 163 clk3 38 a10 80 n.c. 122 ba0 164 n.c. 39 ba1 81 wp 123 a11 165 sa0 40 v dd 82 sda 124 v dd 166 sa1 41 v dd 83 scl 125 clk1 167 sa2 42 clk0 84 v dd 126 a12 168 v dd
hys 64/72v32300gu sdram-modules infineon technologies 4 9.01 block diagram: 32m x 64/72 one bank sdram dimm modules dq0-dq7 dqm we d0 cs0 we dq(7:0) dqmb0 dq0-dq7 dq(39:32) dqmb4 dqm d4 dq0-dq7 dq(15:8) dqmb1 dqm d1 cs dq0-dq7 dq(47:40) dqmb5 dqm d5 dq0-dq7 cb(7:0) dqm cs d8 dq0-dq7 dq0-dq7 dq(31:24) dqmb3 dq(23:16) dqmb2 dqm dqm cs2 cs cs cs d3 d2 dqmb7 dq(63:56) dqmb6 dq(55:48) cs d7 d6 dq0-dq7 dqm dq0-dq7 dqm a0-a12, ba0, ba1 d0-d7, (d8) cc v ss v c0-c15, (c16, c17) d0-d7, (d8) ras d0-d7, (d8) d0-d7, (d8) cas clock wiring 16 m x 64 16 m x 72 clk0 4 sdram + 3.3 pf 5 sdram termination termination clk1 4 sdram + 3.3 pf 4 sdram + 3.3 pf clk2 clk3 47 k scl scl 2 sa0 sa1 sa2 e prom (256 word x 8 bit) sa1 sa0 sa2 sda wp ? cs cs we we we we cs we we we we d0-d7, (d8) cke0 d0-d7, (d8) termination termination note: d8 is only used in the x72 ecc version and all resistor values are 10 ohm except otherwise noted. bl013
hys 64/72v32300gu sdram-modules infineon technologies 5 9.01 absolute maximum ratings parameter symbol limit values unit min. max. input / output voltage relative to v ss v in, v out ? 1.0 4.6 v power supply voltage on v dd v dd ? 1.0 4.6 v storage temperature range t stg -55 +150 o c power dissipation per sdram component p d ? 1w data out current (short circuit) i os ? 50 ma permanent device damage may occur if ? absolute maximum ratings ? are exceeded. functional operation should be restricted to recommended operation conditions. exposure to higher than recommended voltage for extended periods of time affect device reliability dc characteristics t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v parameter symbol limit values unit min. max. input high voltage v ih 2.0 v dd +0.3 v input low voltage v il ? 0.5 0.8 v output high voltage ( i out = ? 4.0 ma) v oh 2.4 ? v output low voltage ( i out =4.0 ma) v ol ? 0.4 v input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0 v) i i(l) ? 40 40 a output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) ? 40 40 a capacitance t a = 0 to 70 c; v dd =3.3v 0.3 v, f =1mhz parameter symbol limit values unit max. 32m x 64 max. 32m x 72 input capacitance ( a0 to a11, ba0, ba1, ras , cas , we ) c i1 65 72 pf input capacitance (cs0 - cs3 ) c i2 32 40 pf input capacitance (clk0 - clk3) c icl 38 40 pf input capacitance (cke0) c i3 65 72 pf input capacitance (dqmb0 - dqmb7) c i4 13 16 pf input/output capacitance (dq0 - dq63, cb0 - cb7) c io 10 10 pf input capacitance (scl, sa0-2) c sc 88pf input/output capacitance c sd 88pf
hys 64/72v32300gu sdram-modules infineon technologies 6 9.01 operating currents per sdram component 1) t a = 0 to 70 o c, v dd = 3.3 v 0.3 v parameter test condition symbol -7.5 -8 unit note max. operating current t rc = t rcmin. , t ck = t ckmin. outputs open, burst length = 4, cl = 3 all banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access ? i cc1 230 170 ma 2) precharge stand-by current in power down mode cs = v ih(min.) , cke v il(max.) t ck =min. i cc2p 22ma 2) precharge stand-by current in non-power down mode cs = v ih (min.) , cke v ih(min.) t ck =min. i cc2n 40 30 ma 2) no operating current t ck = min., cs = v ih(min.) , active state (max. 4 banks) cke v ih(min.) i cc3n 50 45 ma 2) cke v il(max.) i cc3p 10 10 ma 2) burst operating current t ck =min., read command cycling ? i cc4 150 100 ma 2), 3) auto refresh current t ck =min., auto refresh command cycling ? i cc5 240 220 ma 2) self refresh current self refresh mode, cke = 0.2 v i cc6 33ma 2) 1. all values are shown per one sdram component. 2. these parameters depend on the cycle rate. these values are measured at 133 mhz operation frequency for -7 & -7.5 and at 100 mhz for -8 modules. input signals are changed once during t ck , excepts for i cc6 and for stand-by currents when t ck = infinity. 3. these parameters are measured with continuous data stream during read access and all dq toggling. cl = 3 and bl = 4 are assumed and the data-out current is excluded.
hys 64/72v32300gu sdram-modules infineon technologies 7 9.01 ac characteristics 1), 2) t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -7 pc133-222 -7.5 pc133-333 -8 pc100-222 min. max min. max. min. max. clock clock cycle time cas latency = 3 cas latency = 2 t ck 7.5 7.5 ? ? 7.5 10 ? ? 10 10 ? ? ns ns ? system frequency cas latency = 3 cas latency = 2 f ck ? ? 133 133 ? ? 133 100 ? ? 100 100 mhz mhz ? clock access time cas latency = 3 cas latency = 2 t ac ? ? 5.4 5.4 ? ? 5.4 6 ? ? 6 6 ns ns 3), 4) clock high pulse width t ch 2.5 ? 2.5 ? 3 ? ns 4) clock low pulse width t cl 2.5 ? 2.5 ? 3 ? ns 4) setup and hold times input setup time t cs 1.5 ? 1.5 ? 2 ? ns 5) input hold time t ch 0.8 ? 0.8 ? 1 ? ns 5) power down mode entry time t sb ? 1 ? 1 ? 1clk 6) power down mode exit setup time t pde 1 ? 1 ? 1 ? clk 7) mode register setup time t rsc 2 ? 2 ? 2 ? clk transition time (rise and fall) t t 1 ? 1 ? 1 ? ns ? common parameters ras to cas delay t rcd 15 ? 20 ? 20 ? ns ? precharge time t rp 15 ? 20 ? 20 ? ns ? active command period t ras 42 ? 45 100k 50 100k ns ? cycle time t rc 60 ? 67.5 ? 70 ? ns ? bank to bank delay time t rrd 14 ? 15 ? 16 ? ns ? cas to cas delay time (same bank) t ccd 1 ? 1 ? 1 ? clk ?
hys 64/72v32300gu sdram-modules infineon technologies 8 9.01 refresh cycle refresh period (8192 cycles) t ref 64 ?? 64 ? 64 ms 6) self refresh exit time t srex ? 11 ? 1 ? clk 8) read cycle data out hold time t oh 3 ? 3 ? 3 ? ns 2) data out to low impedance t lz 0 ? 0 ? 0 ? ns ? data out to high impedance t hz 373738ns 9) dqm data out disable latency t dqz ? 2 ? 2 ? 2clk ? write cycle data input to precharge (write recovery) t wr 2 ? 2 ? 2 ? clk ? dqm write mask latency t dqw 0 ? 0 ? 0 ? clk ? ac characteristics (cont ? d) 1), 2) t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -7 pc133-222 -7.5 pc133-333 -8 pc100-222 min. max min. max. min. max.
hys 64/72v32300gu sdram-modules infineon technologies 9 9.01 notes 1. all ac characteristics are shown for the sdram components. an initial pause of 100 s is required after power-up. then a precharge all banks command must be given followed by eight auto refresh (cbr) cycles before the mode register set operation can begin. 2. ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown in figure below. specified t ac and t oh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v/ ns edge rate between 0.8 v and 2.0 v. 3. if clock rising time is longer than 1 ns, a time ( t t /2 ? 0.5) ns must be added to this parameter. 4. rated at 1.4 v. 5. if t t is longer than 1 ns, a time ( t t ? 1) ns must be added to this parameter. 6. whenever the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to ? wake-up ? the device. 7. timing is a asynchronous. if setup time is not met by rising edge of the clock then the cke signal is assumed latched on the next cycle. 8. self refresh exit is a synchronous operation and begins on the second positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied after the self refresh exit command is registered. 9. this is referenced to the time at which the output achieved the open circuit condition, not to output voltage levels. serial presence detect a serial presence detect storage device - e 2 prom - is assembled onto the module. information about the module configuration, speed, etc. is written into the e 2 prom device during module production using a serial presence detect protocol (i 2 c synchronous 2-wire bus). 50 pf i/o measurement conditions for t ac and t oh clock 2.4 v 0.4 v input is t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t ih t 1.4 v io.vsd
hys 64/72v32300gu sdram-modules infineon technologies 10 9.01 spd-table for 32m x 64 (256mbyte non-ecc) modules hys64v32300gu byte# description spd entry value hex 32m x 64 -7 -7.5 -8 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses 13 0d 4 number of column addresses 10 0a 5 number of dimm banks 1 01 6 module data width 64 40 7 module data width (cont ? d) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl = 3 7.5 / 10 ns 75 75 a0 10 sdram access time at cl = 3 5.4 / 6 ns 54 54 60 11 dimm config non-ecc 00 12 refresh rate/type self-refresh, 7.8 s 82 13 sdram width, primary x8 08 14 error checking sdram data width na 00 15 minimum clock delay for back-to- back random column address t ccd =1clk 01 16 burst length supported 1, 2, 4 & 8 0f 17 number of sdram banks 4 04 18 supported cas latencies cl = 2 & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes unbuffered 00 22 sdram device attributes: general v dd tol +/ ? 10% 0e 23 sdram cycle time at cl = 2 7.5 / 10.0 ns 75 a0 a0 24 sdram access time at cl = 2 5.4 / 6.0 ns 54 60 60 25 sdram cycle time at cl = 1 not supported 00 ff ff 26 sdram access time at cl = 1 not supported 00 ff ff 27 minimum row precharge time 15 / 20 ns 0f 14 14 28 min. row to row active delay t rrd 14 / 15 / 16 ns 0e 0f 10 29 minimum ras to cas delay t rcd 15 / 20 ns 0f 14 14 30 minimum ras pulse width t ras 42 / 45 / 50 ns 2a 2d 32 31 module bank density (per bank) 256 mbyte 40 32 sdram input setup time 1.5 / 2.0 ns 15 15 20 33 sdram input hold time 0.8 / 1.0 ns 08 08 10 34 sdram data input hold time 1.5 / 2.0 ns 15 15 20 35 sdram data input setup time 0.8 / 1.0 ns 08 08 10
hys 64/72v32300gu sdram-modules infineon technologies 11 9.01 36-61 superset information ? ff ff ff 62 spd revision revision 1.2 12 12 12 63 checksum for bytes 0 - 62 ? f3 36 99 64 manufacturers jedec id code ? c1 65-71 manufacturer infineo(n) 72 module assembly locaction 73-90 module part number 91-92 module revision code 93-94 module manufacturing code 95-98 module serial number 99-125 superset information 126 frequency specification 64 64 64 127 100 mhz support details ? af af af 128+ unused storage locations ? ff byte# description spd entry value hex 32m x 64 -7 -7.5 -8
hys 64/72v32300gu sdram-modules infineon technologies 12 9.01 spd-table for 32m x 72 (256mbyte ecc) modules hys72v32300gu byte# description spd entry value hex 32m x 72 -7 -7.5 -8 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses 13 0d 4 number of column addresses 10 0a 5 number of dimm banks 1 01 6 module data width 72 48 7 module data width (cont ? d) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl = 3 7.5 / 10 ns 75 75 a0 10 sdram access time at cl = 3 5.4 / 6 ns 54 54 60 11 dimm config ecc 02 12 refresh rate/type self-refresh, 7.8 s 82 13 sdram width, primary x8 08 14 error checking sdram data width x8 08 15 minimum clock delay for back-to- back random column address t ccd =1clk 01 16 burst length supported 1, 2, 4 & 8 0f 17 number of sdram banks 4 04 18 supported cas latencies cl = 2 & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes unbuffered 00 22 sdram device attributes: general v dd tol +/ ? 10% 0e 23 sdram cycle time at cl = 2 7.5 / 10.0 ns 75 a0 a0 24 sdram access time at cl = 2 5.4 / 6.0 ns 54 60 60 25 sdram cycle time at cl = 1 not supported 00 ff ff 26 sdram access time at cl = 1 not supported 00 ff ff 27 minimum row precharge time 15 / 20 ns 0f 14 14 28 min. row to row active delay t rrd 14 / 15 / 16 ns 0e 0f 10 29 minimum ras to cas delay t rcd 15 / 20 ns 0f 14 14 30 minimum ras pulse width t ras 42 / 45 / 50 ns 2a 2d 32 31 module bank density (per bank) 256 mbyte 40 32 sdram input setup time 1.5 / 2.0 ns 15 15 20 33 sdram input hold time 0.8 / 1.0 ns 08 08 10 34 sdram data input hold time 1.5 / 2.0 ns 15 15 20 35 sdram data input setup time 0.8 / 1.0 ns 08 08 10
hys 64/72v32300gu sdram-modules infineon technologies 13 9.01 36-61 superset information ? ff ff ff 62 spd revision revision 1.2 12 12 12 63 checksum for bytes 0 - 62 ? 05 48 ab 64 manufacturers jedec id code ? c1 65-71 manufacturer infineo(n) 72 module assembly locaction 73-90 module part number 91-92 module revision code 93-94 module manufacturing code 95-98 module serial number 99-125 superset information 126 frequency specification 64 64 64 127 100 mhz support details ? af af af 128+ unused storage locations ? ff byte# description spd entry value hex 32m x 72 -7 -7.5 -8
hys 64/72v32300gu sdram-modules infineon technologies 14 9.01 package outlines l-dim-168-33 (jedec mo-161-ba) sdram dimm module package note: all tolerances according to jedec standard dimensions in mm l-dim-168-33 133.35 10 11 3 6.35 6.35 41 40 42.18 84 127.35 3 1.27 85 94 95 124 125 168 2 17.78 4 3min. 3 max. 31.75 detail of contacts 2.55 1 1.27 1 1.27 91 x 1.27 = 115.57 3.125 0.25 3 *) on ecc modules only *) + 0.15 - + 0.13 - + 0.1 -
hys 64/72v32300gu sdram-modules infineon technologies 15 9.01
hys 64/72v32300gu sdram-modules infineon technologies 16 9.01 change list: 14.1.1999 input capacitances adjusted 18.4.1999 -8a speed sort added infineon logo added spd codes updated according to new 256m speedsorts 12.5.99 some icc current values changed due to new inputs 21.7.99 hys64/72v32200gu changed to hys64/72v32300gu due to the use of l- dim168-33 instead of l-dim168-30 23.8.99 byte 126 changed to 64h for pc133 modules 6.9.99 template from r&l 29.9.99 some minor errors corrected 20.10.99 cl=2 max. frequency for -7.5 modules changes to 83 mhz 2.12.99 some timing parameters according to intel ? s pc133 specification 20.1.2000 capacitance values for x72 adjusted (new measurements) -8b version removed 10.3.2000 implemented differences between 256mbit s20 and s17 pc133 modules 256mbit s20 based pc133 modules are backward compatible to pc100 3-2-2 256mbit s17 based modules are backwards compatible to pc100-2-2-2 leading to changes in spd code of bytes 23, 63 (checksum) and 126 tpcr issued 10.5.2000 reference to jedec mo-161-ba added 14.02.2001 -8a speedsort removed for 256m s17 and later only 25.07.2001 256m s14 based modules including -7 added 06.09.2001 scr : absolute maximum ratings table added

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